Individual semiconductor devices in VLSI (Very Large Scale Integration) integrated circuits are interconnected by means of one or more patterned conductive layers comprising a high conductivity metal or metal alloy. Advantageously multilevel metal (MLM) interconnect permits crossing over of interconnection paths in different metal layers, to provide for higher density interconnects.
Multilevel metal interconnects for Metal Oxide Semiconductor (MOS) integrated circuit devices are made conventionally by depositing and patterning alternating layers of a conductive material, typically sputtered aluminum alloys such as Al--Si, and layers of an insulating dielectric material, typically SiO.sub.2. Small holes or contact vias through the dielectric layers are filled with conductive material to permit interconnection of the conductive layers. However, the surface topography resulting from superposition of several patterned layers may be highly non-planar. Poor step coverage of the metal layer, particularly within submicron contact holes and vias, or poor coverage of dielectric over edges of the metal, may lead to undesirable high resistance or open circuits.
Furthermore, as device dimensions are scaled down for Ultra Large Scale Integration (ULSI) integrated circuits, interconnect lines are subjected to higher current densities, and electromigration of aluminium alloys becomes a major reliability issue. Other conductive materials which have a higher resistance to electromigration are preferred. For example, tungsten has been used for metal interconnect in submicron Bipolar Complementary MOS (BiCMOS) devices. U.S. Pat. No. 4,954,214 to Ho, entitled "Method for Making Interconnect Structures for VLSI Devices", issued September 1990, describes an improved filled interconnect groove (FIG) method using selective chemical vapour deposition of tungsten or electro-less deposition of nickel or other metals for forming interconnect structures. As described by Ho, tungsten may be deposited with excellent step coverage to fill sub-micron, steep sided, vias and trenches.
However, tungsten has a high resistivity, three times greater than that of Al alloys, which causes a substantial increase in RC interconnect delay. Of other suitable conductive materials, copper has recently been proposed for interconnect for sub half micron integrated circuit devices, because copper has both high electromigration resistance and excellent conductivity. The resistivity of copper is about 60% of the resistivity of Al-alloys.
On the other hand, conventional known methods of depositing copper do not provide satisfactory step coverage for void free filling of high aspect ratio deep trenches and via holes for sub micron device structures. Furthermore, dry etching of copper and copper containing alloys, using conventional plasma or reactive ion etching processes, is hampered by generation of etch products of copper which have a low vapour pressure (i.e. are non-volatile).
For example, U.S. Pat. No. 5,091,339 to Carey entitled "Trenching Techniques for Forming Vias and Channels in Multilayer Electrical Interconnects" issued February 1992, describes electrolytic deposition of copper for filling vias and trenches lined with a seed layer of sputtered copper over an adhesion layer of sputtered chrome, followed by removal of excess copper by electro-polishing or non-selective polishing. Electrolytic deposition of copper suffers from ridge build up over sharp corners of vias and trenches. Thus, a thick blanket layer of copper must be deposited to ensure complete filling of the via holes and trenches of different depths and the resulting surface is highly non-planar. Consequently, a large amount of excess copper from the thick blanket layer must subsequently be removed by a method of electro-polishing or non-selective polishing.
Other known methods of electro-less deposition of copper, for example, as disclosed in Carey, include sputtering or evaporation to obviate the need for a seed layer. Plasma deposition of copper is also known, but as with the latter methods, step coverage is not satisfactory in high aspect-ratio, deep vias and trenches for ULSI integrated circuit structures.
Chemical vapour deposition of copper has also been pursued for filling submicron features with improved step coverage, as described in an article entitled "New OMCVD Precursors for Selective Copper Metallization" by John A. T. Norman et al., 1991 IEEE VMIC Conference Proceedings, Jun. 11-12, 1991, pages 123 to 129. Subsequent etching of the copper layer was achieved by a reverse vapour phase chemical reaction. However, the latter etch method is isotropic, slow and control of planarity is unsatisfactory for commercially etching ULSI device structures.
Apart from limited etch technology, other problems which are encountered in the use of copper for ULSI integrated circuits include copper diffusion through dielectrics, poor adherence of copper to oxide, and surface passivation of copper.